1. Field of the Invention
This invention relates generally to a semiconductor memory device, and, more specifically, to controlling a delay line for achieving power reduction.
2. Description of the Related Art
Modern integrated circuit devices are comprised of millions of semiconductor devices, e.g., transistors, formed above a semiconductor substrate, such as silicon. These devices are very densely packed, i.e., there is little space between them. Similarly densely packed electrically conducting lines may also be formed in the semiconductor substrate. By forming selected electrical connections between selected semiconductor devices and selected conducting lines, circuits capable of performing complex functions may be created. For example, bits of data may be stored by providing electrical current to a plurality of bit lines and an orthogonal plurality of word lines that may be electrically coupled to one or more capacitors in a semiconductor memory.
The semiconductor memory may be a dynamic random access memory, a flash memory, and the like. The semiconductor memory typically comprises an array of memory cells, address decoding circuitry for selecting one, or a group, of the memory cells for reading or writing data, sensing circuitry for detecting the digital state of the selected memory cell or memory cells, and input/output lines to receive the sensed data and convey that information for eventual output from the semiconductor memory. In many cases, the array of memory cells will be sub-divided into several sub-arrays, or subsets, of the complete collection of memory cells. For example, a semiconductor memory having 16 megabits (224 bits) of storage capacity may be divided into 64 sub-arrays, each having 256K (218) memory cells.
Flash memory (sometimes called “flash RAM”) is a type of non-volatile memory that can be erased and reprogrammed in units of memory called blocks. Other types of memory may be erased and rewritten in smaller units, such as units at the byte level, which is more flexible, but slower than the block operations of flash memory. Flash memory is commonly used to hold control code such as the basic input/output system (BIOS) in a personal computer. When BIOS needs to be changed (rewritten), the flash memory can be written in block (rather than byte) sizes, making it faster to update. Applications employing flash memory include digital cellular phones, digital cameras, LAN switches, computers, digital set-up boxes, embedded controllers, and other devices.
Typically, digital systems, such as memory systems, may comprise a delay lock loop that may be used to align the edges of a plurality of digital signals. For example, a delay lock loop circuit may be used to align the rising edge and/or the falling edge of a clock signal based upon a reference clock signal, to produce a synchronized clock signal. Many times, digital signals from multiple sources access one or more memory spaces in a memory unit. It is desirable that these digital signals be synchronized for proper access of memory. Typical delay lock loops comprise a phase detect unit that detects the phase differences between a plurality of signals. The output of the phase detect unit is then used to affect the operation of a filter that adjusts the delay of an output of the delay lock loop. Typical delay lock loop circuits provide a delay block and a delay line (DLL delay line) that implement a delay upon an input clock signal to produce a delayed, output clock signal.
Generally, in the DLL delay line, there is a circuit that includes NAND-gate pairs that provide a fundamental coarse delay element. There may be a plurality of DLL delay lines in a device. Generally, DLL delay lines are designed to toggle only the stages that need to toggle to implement desired delay and synchronization. Therefore, other upstream DLL delay lines do not toggle unnecessarily. This feature is designed into DLL delay circuits for power reduction purposes. Often, there may be 90 or more delay elements in a particular device, wherein only 10 to 20 would toggle at any given time.
In order to achieve equality in propagation times and power savings, “NAND-to-NAND” delay elements are used in DLL circuitry. However, when applying these types of delay elements, device degradation may occur. For example, P-channel elements in various NAND gates that are used in the DLL delay lines may degrade differently from N-channel elements within the NAND gates. The NAND-to-NAND topology is generally used to effectuate an equality in propagation delay that occurs because of the transition from high to low in the first NAND, plus the propagation delay due to the transition from high to low in the second NAND, is assumed to be the same as the low to high propagation in the first NAND plus the high to low propagation. Therefore, the duty cycles, in theory, are designed to be consistent, such that no additive duty cycle error occurs in the clock signal.
However, due to the variations in degradation, one NAND gate may degrade differently from another NAND gate, and therefore, duty cycle errors may occur. If there were a slight duty cycle problem, for example, a pair of NAND gate fundamentally propagating the rising edges faster than the low-going edges, a cumulative effect due to the slight duty cycle error may occur. If this duty cycle problem were to occur in multiple NAND gates, a large duty cycle error may occur. Therefore, one problem associated with
using the NAND-to-NAND topology may be that different propagation delays resulting from a signal transition from high to low time in the NAND versus an inverter may occur. This would negate the various assumptions relating to utilizing NAND-NAND topologies.
Turning now to FIG. 1, a NAND-to-NAND topology is illustrated. FIG. 1 illustrates a first NAND gate 110 and a second NAND gate 120. The proper operation of a delay line represented by the circuit in FIG. 1 depends on the assumptions illustrated by equations 1, 2, and 3. Equation 1 shows an assumption that the high to low transition time for the first and the second NAND gates are equal.tPHL1−tPHL2  EQUATION 1
Equation 2 relates that the low to high transitions for the first NAND gate 110 and the second NAND 120, are equal.tPLH1−tPLH2  EQUATION 2tPHL1+tPLH2=tPLH1+tPHL2  EQUATION 3
Therefore, as illustrated in Equation 3, the addition of the time period for a signal transition from high to low, plus the time period for a signal transition from low to high equals to the time period for a signal transition from low to high for the first NAND gate (110), plus the time period for a signal transition from high to low for the second NAND gate (120). If these were indeed true, the duty cycle of an original clock on a line 105 may be reproduced by the delay line circuit of FIG. 1 on the clock OUT signal on a line 135. However, due to the degradation of various NAND gates, the assumptions provided in Equations 1, 2, and 3, may not hold true. Therefore, this phenomenon may cause a duty cycle error between the difference in the clock IN on the line 105 and the clock OUT on the line 135.
One possible solution to such an additional delay may be that if a duty cycle error is known, for example a duty cycle error of 300 picoseconds is expected, possible corrections could include adding an additional 300 picoseconds delay to the delay line circuit of FIG. 1. However, this creates a problem with dynamic clock applications. The 300 picoseconds delay may depend on the actual frequency of the clock IN on the line 105. If the clock frequency is changed, the additional delay error may change also, leaving the possibility of continued duty cycle errors.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.